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Boundary-Scan Test: A Practical Approach by Harry Bleeker

By Harry Bleeker

The ever-increasing miniaturization of electronic digital parts is hampering the normal checking out of revealed Circuit forums (PCBs) via bed-of-nails furnishings. essentially this is often attributable to the very excessive scale of integration of ICs, by which programs with thousands of pins at very small pitches of all the way down to a fragment of a millimetre, became to be had. in this case the hint distances among the copper tracks on a published circuit board cmne right down to a similar price. not just the necessary small actual dimensions of the try out nails have made traditional checking out unfeasible, but additionally the complexity to supply attempt indications for the various hundreds of thousands of try out nails has grown out of limits. hence a brand new board try method needed to be invented. Following the evolution within the IC try out know-how. Boundary-Scan checking out hm; turn into the hot method of PCB checking out. through taking precautions within the layout of the IC (design for testability), checking out on PCB point will be simplified 10 an excellent volume. This situation has been crucial for the good fortune of the creation of Boundary-Sc,m try (BST) at board level.

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G. synchronization ofthe system clock with TCK). this test method could be unusable for these devices. Therefore the RUNBIST may be best suited (see next subsection). 48 Boun

Test code is enhanced by concurrently sampling signals at chip boundmies. compressing this data ,Uld verifying its signature in-line in the code. lils and showing the advantages of concurrent sampling. some relevant properties of the tmditionally used assembly and functional test methods are summarized. Assembly testing should be performed before functional testing. because the majority of board defects (opens. shorts or wrong components) are assembly related. Boundary-Scan test technology may he used very efficiently in conjunction with 51 52 Boundary-Scan Test: A Practical Approach analogue structural testing such as MDA (Manufacture Defect Analysis).

The TDO signal of the Output cell is connected to the TDI of the Control cell. In this way the TDIffDO serial shift-register path is maintained. But other internal connections between the two cells are also possible. --I- output pin Output cell TOI From last cell Fig. g. connected to a bus) it is allowable to control the respective enable stages with one Boundary-Scan cell. Figure 2-21 shows an example. 3 ~ BS 8 E e cell - I- I LL BS cell - EN I- "- EN V -- 3-state output V - 3-state output lTDI Fig.

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